Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Verilog: grammar for unique case and unique if #446

Merged
merged 1 commit into from
Apr 23, 2024
Merged

Verilog: grammar for unique case and unique if #446

merged 1 commit into from
Apr 23, 2024
+73 −13

Conversation

kroening
Copy link
Member

This adds the Verilog grammar rules for unique case and unique if.

@kroening kroening marked this pull request as ready for review April 20, 2024 23:24
@tautschnig
Copy link
Collaborator

Requires a rebase to resolve conflicts.

@kroening
Verilog: grammar for unique case and unique if
87c8f5a 
This adds the Verilog grammar rules for unique case and unique if.
@kroening
Copy link
Member Author

done

@tautschnig tautschnig merged commit 6e0ac27 into main Apr 23, 2024
5 checks passed
@tautschnig tautschnig deleted the unique_case1 branch April 23, 2024 07:52
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@tautschnig tautschnig tautschnig approved these changes

Assignees
No one assigned
Labels
Verilog
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@kroening @tautschnig